ARCHITECTURE (3145B)
1 TISCv2.3 (c) Paul Longtine <paul@nanner.co> 2 Tiny Instruction Set Computer 3 4 __________ ___ ________ ________ 5 |\___ ___\ |\ \ |\ ____\ |\ ____\ 6 \|___ \ \_| \ \ \ \ \ \___|_ \ \ \___| 7 \ \ \ \ \ \ \ \_____ \ \ \ \ 8 \ \ \ \ \ \ \|____|\ \ \ \ \____ 9 \ \__\ \ \__\ ____\_\ \ \ \_______\ 10 \|__| \|__| |\_________\ \|_______| v2.3 11 \|_________| 12 13 -----------------------------------------------------------------------<-------- 14 The Architecture of TISC 15 -----------------------------------------------------------------------<-------- 16 17 The basic architecture of TISC resembles a Von-Neumann architecture with a an 8-bit 18 address space and an 8-bit word. The execution of instructions and input data is 19 conditionally sourced from external input or internal RAM. Internally the data loop 20 has two primary busses: Register Input bus, and the ALU Output bus. 21 22 There are a total of 10 busses with 7 distinct busses which compose to allow data 23 to move through the architecture. 24 25 The 7 distinct data busses (in no particular order) are as follows: 26 27 0* ALU Output Bus 28 1* Stack Output Bus 29 2* Immediate Bus 30 3* Program Counter Output Bus 31 4* Memory Pointer Bus 32 5* Memory Output Bus 33 6* External Input Bus 34 35 The 3 multiplexed data busses are as follows: 36 37 7* The Register Input bus is multiplexed from 4 busses: 38 0* ALU Output Bus 39 1* Stack Output Bus 40 2* Immediate Bus 41 9* Internal Input Bus 42 43 8* The Address Bus is multiplexed from 2 busses: 44 3* Program Counter Output Bus 45 4* Memory Pointer Bus 46 47 9* The Internal Input Bus is multiplexed from 2 busses: 48 5* Memory Output Bus 49 6* External Input Bus 50 51 These multiplexed busses support the modularity of the system to implement external 52 instruction memory and external memory mapped components to extend the capacity of 53 a TISC core by controlling the source of each multiplexed bus. 54 55 -----------------------------------------------------------------------<-------- 56 External Interface 57 -----------------------------------------------------------------------<-------- 58 59 TISC is structured to be exensible through I/O context and persisting a common core 60 across implementations 61 62 The external interface of TISC has 8 distinct input/output ports 63 64 IO ACTIVE: boolean output 65 Raised when there is an externally mapped address currently selected to support 66 memory mapped IO. 67 Known internally as the "External Address Select". The default address range 68 is 0xFC - 0xFF as memory mapped I/O ports. 69 70 IO ENABLE: boolean input 71 External components raise this line to signal that the external INPUT line can be used 72 73 WRITE ACTIVE: boolean output 74 Raised when there is a write operation for the selected external component. 75 76 INPUT: 8-bit input bus 77 This is the 8-bit bus for incoming data from outside of the TISC core 78 79 OUTPUT: 8-bit output bus 80 This is the 8-bit bus for outgoing data routed to outside of the TISC core 81 82 ADDRESS: 8-bit output bus 83 The current 8-bit program counter value, used to signal for external memory mapped IO 84 85 CLOCK: sync. signal 86 core clock line 87 88 RESET: sync. signal 89 reset core 90 91 92 93 94 95