2023-03-03 05:26 | Update some screenshots, a README file, and tisc debug output format | Paul Longtine | 10 | +2149 | -2168 |
2022-06-23 06:28 | TISCv2.3 Utilized mode of `sp`, `lb`, `sb` instructions to use the stack | Paul Longtine | 15 | +2070 | -1855 |
2022-06-21 20:33 | TISCv2.2 Revised `pcr` instruction, included new `peek` instruction | Paul Longtine | 13 | +1936 | -1928 |
2022-06-21 06:54 | TISCv2.1 Added support for calling/returning from subroutines | Paul Longtine | 12 | +1908 | -1635 |
2022-06-20 11:39 | Updated / added version numbers | Paul Longtine | 2 | +11 | -12 |
2022-06-20 02:29 | More prettify | Paul Longtine | 1 | +82 | -89 |
2022-06-20 02:15 | Prettify some bit of the circuit | Paul Longtine | 1 | +10 | -11 |
2022-06-20 01:46 | Fix use of uninitialized memory | Paul Longtine | 1 | +5 | -0 |
2022-06-20 01:39 | Fix missing calls to `free` | Paul Longtine | 1 | +6 | -0 |
2022-06-20 01:23 | TISCv2.0 Revised immediate system to support loading multiple bytes | Paul Longtine | 12 | +2207 | -1894 |
2022-06-18 21:32 | TISCv1.4 Implement a "write active" pin | Paul Longtine | 7 | +1710 | -1654 |
2021-12-22 03:26 | Modified behavior of `LUI` to AND over OR operation if the last instruction was | Paul Longtine | 3 | +1844 | -1493 |
2021-01-27 23:37 | Merge branch 'fixMissingFree' | Paul Longtine | 1 | +3 | -0 |
2021-01-27 23:36 | Fix missing call to 'free' | Paul Longtine | 1 | +3 | -0 |
2021-01-27 07:37 | Add base 2 and base 16 integer representations for intermediate values | Paul Longtine | 2 | +28 | -2 |
2021-01-17 08:21 | Merge branch 'master' | Paul Longtine | 0 | +0 | -0 |
2021-01-17 07:47 | Multiplexed what was the ADD instruction to use the set operation for compare. | Paul Longtine | 13 | +1872 | -1578 |
2021-01-17 07:47 | Multiplexed what was the ADD instruction to use the set operation for compare. | Paul Longtine | 13 | +1871 | -1577 |
2020-06-18 05:21 | Implemented features to distinguish memory load / save from instruction execution, so that the entire first-class address range is available | Paul Longtine | 1 | +1543 | -1485 |
2020-06-17 06:57 | Added a new test program, some minor modifications to the circuit to fix bugs, and updated the README and documentation a bit | Paul Longtine | 5 | +1457 | -1266 |
2020-06-16 07:36 | Update label and add friendly screenshot to README | Paul Longtine | 3 | +3 | -1 |
2020-06-16 07:27 | Added heaps of documentation, added a new instruction, and trimmed a lot of the excess off of the instruction set decoder | Paul Longtine | 17 | +1901 | -4178 |
2020-06-15 03:29 | Added new comparison operators! Also made string compares less sketchy. | Paul Longtine | 7 | +6773 | -6323 |
2019-09-30 03:39 | Made prettier | Paul Longtine | 2 | +1984 | -1992 |
2019-09-29 19:38 | Fixed bugs, implementing some test programs to shake things down | Paul Longtine | 6 | +1973 | -1917 |
2019-09-28 04:55 | Modularized the logisim implementation of TISC, added a null GPR token in the assembler and re-worded and clarified the INSTRUCTION_SET document | paul_longtine | 3 | +200 | -97 |
2019-09-28 03:31 | Implemented tidy formatting for logisim memory load file, greatly improved niceness of tisc CPU | paul_longtine | 4 | +6182 | -6136 |
2019-09-25 03:49 | Use tabs everywhere, previous commit had mixed tabs and spaces | paul_longtine | 1 | +46 | -46 |
2019-09-25 03:43 | Made headway on implementing instructions. Updated behavior of the SB/LB instructions - do not increment the PC when loading a different address to read/write from memory | Paul Longtine | 3 | +2074 | -1897 |
2019-06-13 20:39 | Line numbering now happy, addressing now happy, and we're producing bytes at this rate. | | 2 | +143 | -88 |
2019-06-13 04:25 | Hashing out tiny assembler | Paul Longtine | 2 | +151 | -93 |
2019-06-12 20:55 | Added TISC CPU | paul_longtine | 9 | +6192 | -7 |
2014-12-20 01:38 | aaaaa | Paul Longtine | 1 | +31 | -38 |
2014-12-19 23:27 | add the thing | Paul Longtine | 1 | +226 | -0 |
2014-12-19 23:25 | Initial commit | Paul Longtine | 1 | +29 | -0 |