tisc

tiny instruction set computer
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DateCommit messageAuthorFiles+-
2020-06-18 05:21Implemented features to distinguish memory load / save from instruction execution, so that the entire first-class address range is availablePaul Longtine1+1543-1485
2020-06-17 06:57Added a new test program, some minor modifications to the circuit to fix bugs, and updated the README and documentation a bitPaul Longtine5+1457-1266
2020-06-16 07:36Update label and add friendly screenshot to READMEPaul Longtine3+3-1
2020-06-16 07:27Added heaps of documentation, added a new instruction, and trimmed a lot of the excess off of the instruction set decoderPaul Longtine17+1901-4178
2020-06-15 03:29Added new comparison operators! Also made string compares less sketchy.Paul Longtine7+6773-6323
2019-09-30 03:39Made prettierPaul Longtine2+1984-1992
2019-09-29 19:38Fixed bugs, implementing some test programs to shake things downPaul Longtine6+1973-1917
2019-09-28 04:55Modularized the logisim implementation of TISC, added a null GPR token in the assembler and re-worded and clarified the INSTRUCTION_SET documentpaul_longtine3+200-97
2019-09-28 03:31Implemented tidy formatting for logisim memory load file, greatly improved niceness of tisc CPUpaul_longtine4+6182-6136
2019-09-25 03:49Use tabs everywhere, previous commit had mixed tabs and spacespaul_longtine1+46-46
2019-09-25 03:43Made headway on implementing instructions. Updated behavior of the SB/LB instructions - do not increment the PC when loading a different address to read/write from memoryPaul Longtine3+2074-1897
2019-06-13 20:39Line numbering now happy, addressing now happy, and we're producing bytes at this rate.2+143-88
2019-06-13 04:25Hashing out tiny assemblerPaul Longtine2+151-93
2019-06-12 20:55Added TISC CPUpaul_longtine9+6192-7
2014-12-20 01:38aaaaaPaul Longtine1+31-38
2014-12-19 23:27add the thingPaul Longtine1+226-0
2014-12-19 23:25Initial commitPaul Longtine1+29-0