tisc

commit fc6eafdc05524e527aeefe728e0700b648dfdcba
parent bddc146e813f6851ba1ecca6a66d288869b2bdf0
Author: Paul Longtine <paul@nanner.co>
Date:   Tue, 16 Jun 2020 03:36:15 -0400

Update label and add friendly screenshot to README

Diffstat:
M
CPU/CPU.circ
 | 
2
+-
M
README.md
 | 
2
++
A
Screenshots/tiscv1_2.png
 | 
0

3 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/CPU/CPU.circ b/CPU/CPU.circ
@@ -242,7 +242,7 @@
       <a name="facing" val="north"/>
     </comp>
     <comp lib="6" loc="(303,244)" name="Text">
-      <a name="text" val="TISCv1.0"/>
+      <a name="text" val="TISCv1.2"/>
       <a name="font" val="Dialog plain 14"/>
     </comp>
     <comp lib="6" loc="(290,239)" name="Text"/>
diff --git a/README.md b/README.md
@@ -3,6 +3,8 @@
 This is a for-fun implementation of a relatively simple microarchitecture, with
 an assembler to program the simulated implementation in [Logisim](http://www.cburch.com/logisim/).
 
+![TISC v1.2](Screenshots/tiscv1_2.png)
+
 ## Want to play with it too?
 
 To compile the assembler, run tisc.c through GCC:
diff --git a/Screenshots/tiscv1_2.png b/Screenshots/tiscv1_2.png
Binary files differ.